The present invention is in the field of serial data transmission as it applies to computerized semiconductor devices and pertains more particularly to methods and apparatus for achieving high speed serial data transmission between semiconductor devices.
The art of designing and implementing very large scale integration (VLSI) devices has become more complex and sophisticated in recent years. Sophisticated software design tools and automated techniques have replaced prior pencil and paper engineering practices once used to design semiconductor devices. As VSLI devices have become more complex in terms of circuitry and design with shrinking device geometry, requirements for data transmission between such devices have also become more complex and demanding to maintain in operation.
The preferred system used for data transmission between VLSI and other IC devices has long been the system of parallel data transfer. The current parallel method of passing data between such devices incorporates the use of a plurality of separate data-signal transmission paths in parallel. Data passed between two communicating devices travels across a circuit board on a plurality of parallel traces or lines. For a 16-bit system, for example, there will be in a parallel system a separate trace for each bit (16 traces) plus control lines.
Generally speaking, much operational and specification data regarding the manufacture and operation of VLSI type devices is known and available in the art. Manufacturers of such devices provide exhaustive documentation, and virtually all such documentation are available to the skilled artisan. Therefore detailed architectural and functional descriptions of known VLSI-type devices are not provided herein. It is enough to say that parallel data must be clocked, synchronized and latched in order to enable successful transmission of the data from a propagating device to a receiving device over a circuit board containing a substantially large number of traces.
Another system for transferring data in general, and also sometimes used for transferring data between IC devices the serial system. The current art serial method of transferring high bandwidth data between VLSI devices involves the use of encoding and decoding circuits on each device to manipulate parallel data so that it may be transmitted serially across a circuit board from one device to another. For example, a parallel to serial data converter in a sending device enables data to be prepared for transmission out in a serial manner using a single data line for one-way transmission. A decoder circuit in a receiving device decodes the serial data using a predetermined decoding scheme then processes the data. Because, given a single clock speed for both, serial data transfer is typically slower than parallel transfer, a high-speed clock is typically used with the serial system to speed up transmission of serial data between devices.
Another problem with serial data transfer between IC devices in current technology is that analog circuitry is typically required in the IC devices to effect the system. Analog circuitry is known to be notoriously more difficult to implement than digital circuitry, and makers of digital IC devices are not anxious to suffer the yield losses attendant on adding analog circuitry to their devices.
Still, even with the known and perceived disadvantages of serial data transmission, the high cost and complexity of parallel systems is an increasing problem. As computing systems have matured from 4 to 8 to 16 to 32 bit words, and as microprocessors and memories (for example) have become more functional and sophisticated, the number of traces and pins necessary to accomplish adequate transmission has increased dramatically. It is, for example, common now to have plural sets of parallel data transmission pathways serving a single IC device. The high number of traces necessary on a PC board (for example) makes such support systems enormously complex and expensive to design and manufacture. Moreover, every trace demands a separate pin on the IC device. Many devices have more than two hundred pins, and future devices may demand even more. The higher and higher pin count makes such devices more complex to build and increases losses (yield) in fabrication.
Another limitation relates to precious design space. For example, increasing the number of parallel devices complicates the physical connection scheme between a propagating device and a receiving device on a circuit board. Furthermore, the propagation delay of each data path from line to line must be kept common to ensure successful data reception. Adding to many traces may cause a significant variance in individual propagation delays leading to errors in data flow.
Other problems associated with adding additional data traces to facilitate parallel transmission of more data over a shorter period include increased electromagnetic emissions to adjacent circuitry and increased power requirements needed to support the hardware. Increased emissions may infect adjacent signal lines causing noise and increasing the possibility of data errors. Increasing power requirements reduces chip reliability and may require additional power-dissipation devices to be included in chip manufacture.
It is a goal in chip design to be able to transmit more data at higher rates. However, achieving this objective using parallel data transfer techniques creates complexity and added cost. It is well known that the current-art serial methods reduce the number of required data traces for data transmission. However, the complex analog circuitry required to achieve a comparable result with the parallel method at higher clock speeds presents technical obstacles related to the complex nature of the added circuitry, which ultimately lends leads to error prone data transmission.
Therefore, what is clearly needed is a method and apparatus that enables a high-speed serial intercommunication between VLSI and other semiconductor devices, fast enough to compete with at least present day parallel systems, and in a manner to overcome the complex issues in the art described above. Such a method and apparatus will provide a serial data transmission system that is competitive to the parallel system at high clock speeds, and will reduce the design complexity related to the physical connection scheme required between devices.
In a preferred embodiment of the present invention a serial data communication system for communication between a first and a second IC device is provided, comprising a separate master chip connected to both the first and to the second IC devices, the master chip comprising a clock generator and circuitry for affecting serial data transmission and control between the master chip and the first and second IC devices; and a slave component on each IC device for transforming data between parallel and serial data formats and for sending and receiving a serial data stream. The master chip provides a clock signal to both slave components for gating serial data communication, and manages all communication between the two slave components. Preferably all circuitry in the slave components is digital circuitry, and all analog circuitry is implemented on the master chip.
In one embodiment of the invention each slave component sends a serial data stream to the master chip for transfer to the opposite slave component, receives serial data stream from the master chip provided by the opposite slave component, and compares phase between the serial data stream received and the clock signal. Upon detecting a phase difference between the clock signal and the serial data stream received, each slave component sends a correction code in the serial data stream sent to the master chip, the correction code indicating a correction in phase to be made between the clock signal and the serial data stream received by the slave component. Upon receiving the correction code the master chip causes a correction to be made in the phase between the clock signal and the serial data stream being sent to the slave component sending the correction code.
In preferred embodiments of the invention each slave component inserts a correction code in the serial data stream being sent to the master chip at a fixed period in the data stream, regardless of phase difference detected, and adjusts the code sent according to the phase difference detected, if any. To insert the correction code in the serial data stream being sent to the master chip, the slave component stops propagation of the serial data stream momentarily, causing data to be absorbed in a first-in-first-out (FIFO) buffer while the correction code is inserted.
In preferred embodiments the slave components comprise a multiplexer (mux) for parallel to serial data conversion, the mux taking parallel data from the associated IC device and converting the parallel data to serial data, and the FIFO buffer is placed ahead of the mux to handle parallel rather than serial data. Each slave component receives serial data from the master chip, decodes the data and removes the correction codes, and processes the serial data via a demultiplexer to convert the serial data to parallel data for the associated IC device.
In another aspect of the invention a slave circuitry for inclusion on a digital IC chip is provided, comprising a data-in serial port and a data-out serial port for exchanging serial data with a master chip; a clock in port for receiving a clock stream from the master chip; and a phase comparator for determining phase difference between the clock stream received and serial data received at the data-in port. There is preferably a multiplexer (mux) for converting parallel data from an IC chip upon which the slave circuitry is implemented to serial data, an encoder circuit in the serial data stream from the mux, and a driver after the encoder for driving the serial data out the data-out port, wherein the encoder places a correction code periodically in the serial data stream, the correction code selected according to phase error determined by the phase comparator. There is preferably a first-in-first-out (FIFO) buffer before the mux, wherein the encoder stops the serial data stream to the data-out port while inserting the correction codes, and parallel data is buffered in the FIFO. There may also be a decoder circuit coupled to the data-in port and a demultiplexer (demux) coupled to the decoder circuit, wherein the decoder circuit strips correction code from serial data received at the data-in port, and the demux converts the serial data received to parallel data for the IC device on which the slave circuitry is implemented.
In yet another aspect of the invention a master serial data communication chip is provided, comprising a clock generator coupled to first and second clock-out ports; a first data-in port coupled to a first data out port through first serial retiming circuitry; and a second data-in port coupled to a second data-out port through second serial retiming circuitry. The master chip receives a first serial data stream at the first data-in port from a first slave component on a first IC device, retimes and sends the first serial data stream on to a second slave component on a second IC device via the first data-out port, receives a second serial data stream at the second data-in port from the second slave component on the second IC device, retimes and sends the second serial data stream on to the first slave component on the first IC device via the second serial retiming circuitry, and sends a common clock stream to the first and second slave components via the first and second clock-out ports.
In the master chip there is preferably a first correction code detect circuit connected to the first data-in port and to a first phase adjust circuit also connected to the first clock out port, and a second correction code detect circuit connected to the second data-in port and to a second phase adjust circuit also connected to the second clock out port, wherein the respective code detect circuits detect correction codes sent by the respective slave components and cause the phase adjust circuits to adjust the clock streams to correct phase between data-out and clock to each slave component according to incoming correction codes.
In the master chip the first serial retiming circuitry may have first phase lock, phase adjusting, and retiming circuitry, and the second serial retiming circuitry may have second phase lock, phase adjusting and retiming circuitry such that data in in each direction is retimed and phase locked with clock out and data out in the same direction, the master chip thus managing data from one IC device to the other in each direction.
In yet another aspect of the invention a method for accomplishing serial data transfer between two IC devices is provided, comprising steps of (a) managing serial data streams between the two IC devices, each device having serial data receiving and sending slave circuitry, through a central master chip; and (b) supplying a common clock signal for the receiving and sending circuitry on the two IC devices from the central master chip. In this method preferably the master chip phase locks and retimes data received from one slave circuit before sending the data stream to the other slave component, and each slave circuitry determines phase offset between clock signal received from the master chip and serial data received from the master chip, and inserts a correction code in serial data sent back to the master chip. The master chip then receives the correction codes and corrects phase accordingly between data streams and clock streams sent to each slave circuitry.
In still another embodiment a method for cost-effectively providing serial communication between two IC devices is provided, comprising steps of (a) implementing multplex, demultiplex, driver, and receiver circuitry in slave circuit modules on each of the two IC devices entirely in digital circuitry; and (b) connecting the two slave circuit modules through a master chip incorporating all necessary digital circuitry for the serial communication. In this method there may be a further step for (c) sending a common clock signal to the two slave circuit modules from the master chip.
In the embodiments of the present invention taught in enabling detail below, for the first time a serial communication system is provided in the art wherein IC manufacturers may implement serial chip-to-chip communication without suffering the expense of including analog circuitry on the expensive and complex IC devices, which historically increases yield losses.